Compression-based SoC Test Infrastructures
نویسندگان
چکیده
Test Data Compression techniques have been developed for reducing requirements in terms of Automatic Test Equipments. In this paper, we explore the benefits of using these techniques in the context of core-based SoCs. Test Data Compression is used to reduce the system test time by increasing the test parallelism of several cores without the expense of additional tester channels. In this paper, we first discuss the constraints on test architectures and on the design flow inferred by the use of compressed test data. We propose a method for seeking an optimal architecture in terms of total test application time. The method is independent of the compression scheme used for reduction of core test data. The gain in terms of test application time for the SoC is over 50% compared to a test scheme without compression.
منابع مشابه
A Two-level Simultaneous Test Data and Time Reduction Technique for SOC
A two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced...
متن کاملAutomating IEEE 1500 Core Test—An EDA Perspective
THE CURRENT TREND of SoC design has made conventional test methodologies increasingly difficult. Performing brute-force test pattern generation (ATPG) on the entire SoC is often infeasible, because the design can exceed the test pattern generator’s capabilities. At other times, some black-box third-party cores within the SoC might have their own test patterns generated at the core boundary. IEE...
متن کاملOn Dictionary based Test Data Compression
Test data volume is now recognized as a major contributor to the cost of SoC manufacturing testing, as it leads to an increasing testing time. In this paper we present the progress of the dictionary based test data volume reduction (compression) methods.
متن کاملOptimization of Scan Time of Scan Test in System-on-chip
We present an SoC testing approach that integrates test data compression, T AM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as the compression engine. All cores on the SoC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits from the test cube...
متن کاملA hybrid test compression technique for efficient testing of systems-on-a-chip
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and ...
متن کامل